The present invention relates to a semiconductor apparatus (or semiconductor integrated circuit) having a clock generating circuit for generating an internal clock signal synchronized with a clock signal entered from outside, and more particularly to a clock generating circuit for generating an internal clock signal whose timing error occurring with a clock signal entered from outside is infinitesimal and to the application of a clock signal formed by the clock generating circuit to a semiconductor apparatus.
References referred to in this specification are the following:
{REF 1} 1993 International Solid-State Circuit Conference Digest of Technical Papers, pp. 160-161, February 1993;
{REF 2} 1994 International Solid-State Circuit Conference Digest of Technical Papers, pp. 300-301, February 1994;
{REF 3} Japanese Patent Laid-open No. 8-23709 (counterpart U.S. Pat. No. 5,699,003);
{REF 4} Japanese Patent Laid-open No. 10-126254.
These references will be referred to below by their respective reference numbers.
As clock recovery circuits for generating an internal clock synchronized in phase with an external clock, phase locked-loop (PLL) and a delay-locked loop (DLL) circuits are known, as disclosed in {REF1} and {REF2}, respectively. Since these circuits are feedback circuits, they take a relatively long time for phase matching.
Known clock recovery circuits to shorten the time required for phase matching include so-called synchronous mirror delay (SMD) circuits disclosed in {REF 3} and {REF 4}.
The SMD circuit described in {REF 3} comprises a first delay circuit array for generating a plurality of reference clock arrays from a standard clock; a control circuit for comparing the plurality of reference clock arrays with the standard clock to select and pass a reference clock close in phase to the standard clock; and a second delay circuit array for adding to the clock selected by the control circuit delays equal to the number of delay stages passed in the first delay circuit array. As a consequence, the accuracy of phase synchronization of the SMD circuit is determined by the delay time per stage of delay circuit. FIGS. 12 and 13 of {REF3} show a variable delay circuit for performing adjustment by an integral multiple of a delay time shorter than that of the delay circuits of the SMD circuit at a time into the input section of the first delay circuit array of the SMD circuit. The delay time of this variable delay circuit is under feedback control by a standard clock entered into the delay circuit, an internal circuit formed by the second delay circuit, an array coupled to the SMD circuit, and a phase comparator.
The present inventors studied a synchronous DRAM (SDRAM) for delivering and receiving data in synchronism with a clock signal entered from outside as a high speed dynamic random access memory (DRAM). As its operating frequency is enhanced and the clock cycle time reduced, the clock access time from the entry of the external clock until the outputting of data poses a problem, because the clock access time should be sufficiently shorter than the clock cycle time in order to secure a time for the data read out of the SDRAM to be set up. In this connection, a clock generating circuit (which may as well be called a clock recovery circuit) for generating an internal clock within the SDRAM from the external clock signal is important for high speed operation.
Subjects for a clock generating circuit to be required f or the above mentioned application are the following. (1) The lock-in time taken to generate an internal clock from an external clock again, with the external clock being temporarily intercepted, should be sufficiently short to place the SDRAM in a low power consumption mode. (2) While reducing the lock-in error between the external and internal clocks, the lock-in time until generating the internal clock should be sufficiently short. (3) Power consumption by the clock recovery circuit should be low. (4) Both the dimensions of the circuit and the area it occupies on the semiconductor substrate should be small.
In spite of these requirements, the DLL and the PLL described in {REF 1} and {REF 2}, though they have the advantages that the internal clock is generated with high accuracy (with little lock-in error) and that they involve little jitter problem, take a relatively long time for the internal clock to be recovered. The circuit illustrated in FIG. 12 of {REF 3} seems susceptible to little lock-in error of the internal clock if it operates ideally because it has both an SMD circuit and a variable delay circuit for fine tuning. However, no consideration is given to the stability of the system in this circuit, wherein each of the SMD circuit and the fine-tuning variable delay circuit has its own independent feedback path.
An object of the present invention is to maintain the stability of the clock recovery circuit and shorten the lock-in time until the generation of the internal clock while reducing the lock-in error between the external and internal clocks.
Another object of the invention is to shorten the lock-in time taken when the external clock is temporarily intercepted and the internal clock is generated from the external clock.
Still another object of the invention is to reduce the circuit area and power consumption by the clock recovery circuit.
In order to achieve the foregoing objects, a typical configuration of a semiconductor integrated circuit according to the invention, includes a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises an input standard node, to which said external clock is coupled, for supplying a first standard clock; a plurality of first delay circuits, whose initial stage is coupled to said input standard node, for supplying a plurality of reference clocks differing in phase from each other; a comparator for detecting a predetermined number of delay stages required for locking in by comparing the plurality of reference clock arrays with said first standard clock and detecting the reference clock closest in phase to said standard clock; a control circuit having a latch circuit for holding information on said predetermined number of delay stages; a plurality of second delay circuits each having an input node into which said first standard clock is entered via a switch; and an output standard node, which is coupled to the final stage of said second delay circuits, for supplying said internal clock, wherein said internal clock is formed by causing said first standard clock to be entered into said input node of the corresponding one of said plurality of second delay circuits to said predetermined number of delay stages, detected by said control circuit.